1. Field of the Invention
The invention relates to electronic devices with a high dielectric constant (high-k) dielectric layer, and in particular to electronic devices with high-k dielectric including combinations of organic and/or inorganic hybrid high-k dielectric material and fabrication methods thereof.
2. Description of the Related Art
Operation of a field effect transistor (FET) is due to enough charges being induced at the interface between the semiconductor and gate insulating layer. In order to generate high current ID at low operating voltage, the FET requires high carrier mobility in its semiconductor layers, high width-to-length ratio of its channels as well as high capacitance of the FET structure. High capacitance of the FET structure depends on the thickness and dielectric constant (k) of the gate insulating layer. A thinner high-k gate insulating layer results in a high current ID at low operating voltage, thereby reducing power consumption.
U.S. Pat. No. 6,586,791, the entirety of which is hereby incorporated by reference discloses a method for forming a gate insulating layer. A suspension solution is prepared by dispensing nano-scale ceramic particles in a polymer solution. The suspension solution is then applied on a substrate by spin coating, thus forming a gate insulating layer. The gate insulating layer prepared by the conventional method, however, suffers from rough surfaces, strip defects and unevenness, resulting in high leakage in electronic devices during operation.
FIG. 1 is a cross section of a conventional organic thin film transistor (OTFT) device formed by dispensing nano-scale ceramic particles in a polymer solution. Referring to FIG. 1, an OTFT includes a heavily doped silicon substrate 10 with a metal layer 15 disposed thereon to served as a gate electrode. An insulating layer 20 is formed on the heavily doped silicon substrate 10. A source region 25 and a drain region 30 separated by a predetermined distance are formed on the insulating layer 20. An organic semiconductor layer 35 is disposed on the heavily doped silicon substrate 10 and covers the source region 25, the drain region 30, and the region therebetween. Since the insulating layer 20 is typically formed by spin coating a suspension solution and dispensing nano-scale ceramic particles in a polymer solution, the insulating layer 20 suffers from rough surfaces, strip defects and unevenness, i.e., the peak-to-valley can reach 0.3 μm for film thicknesses less than 0.6 μm, resulting in high leakage in the electronic device during operation.
U.S. Pat. No. 6,558,987, the entirety of which is hereby incorporated by reference discloses a thin film transistor (TFT) device and fabrication methods thereof. Two dielectric layers are used as a gate dielectric of a conventional TFT device. Both dielectric layers such as silicon nitride (SiNx) or silicon oxide (SiOx) respectively, are inorganic materials deposited by chemical vapor deposition (CVD). After a first dielectric layer is deposited, contaminant residue on the first dielectric layer is cleaned. A second dielectric layer is then deposited on the first dielectric layer to avoid defect generation.
U.S. Pat. No. 6,563,174, the entirety of which is hereby incorporated by reference discloses two high-k dielectric layers used as a gate dielectric of the conventional TFT device, wherein a first dielectric layer is typically silicon nitride (SiNx), while the second dielectric layer is a metal oxide such as BaTiO3, CaZrO3, or SrSnO3. The second dielectric layer improves crystallinity of the semiconductor layer (e.g., ZnO) to improve carrier mobility of the TFT devices.
U.S. Pat. No. 7,005,674, the entirety of which is hereby incorporated by reference discloses an organic thin film transistor (OTFT) structure and fabrication method thereof. Two organic dielectric layers are used as a gate dielectric of the OTFT device, wherein the first dielectric layer is a high-k dielectric layer, and the second dielectric layer is a polymer covering the first dielectric layer, thereby matching the semiconductor of the OTFT device and improving performance of the device.
FIG. 2 is a cross section of another conventional organic thin film transistor (OTFT) device. Referring to FIG. 2, an organic thin film transistor includes a substrate 50 with a gate electrode 55 thereon. A first insulating layer 60 is disposed on the substrate 50 covering the gate electrode 55. A second insulating layer 65 is disposed on the first insulating layer 60. An organic semiconductor layer 70 is disposed on the second insulating layer 65. A source region 80 and a drain region 90 separated by a predetermined distance are formed on the organic semiconductor layer 70. Although the second insulating layer can improve original interface properties between the organic semiconductor layer 70 and the high-k first dielectric layer 65, due to the rough interface between the second insulating layer 65 and the first insulating layer 60, high leakage for electronic devices during operation often occur. Thus, decreasing performance efficiency.
The aforementioned conventional OTFT devices include a two-layered dielectric structure as the gated dielectric layer of the OTFT device. The dielectric constant of the second dielectric layer is typically lower than that of the first dielectric layer such that increasing the dielectric constant is limited. Thus, limiting applications of the OTFT devices.